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Reply To: High SD drop

Da Architect



you may chech the following:
1. sdcch congestion versus paging congestion
2. paging load (you might need to modify MFRMS and AG BLK RES)
3. LAC of certain cells defined correctly in NSS and BSS, in other words, you might need to check this area per LAC, has it’s adjacent LAC defined in NSS
4. ATT parameter
5. correct plan of RAC/LAC
6. BSC/LAC design

This is what I can remember for now.