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Reply To: Abis configuration for EDGE



there is a major difference between NJ and Sheldon computations.
NJ assumes that 1 TRX uses 2 full Abis TS (= 8 Abis nibbles).
Sheldon assumes that 1 TRX uses only as many Abis nibbles as the number of TCH on that TRX. For examlple 1 TRX with 1 BCCH + 1 SDCCH + 6 TCH would use only 6 abis nibbles = 1.5 Abis timeslot.

Both could be true, because it only depends on the E/// implementation.
In ALU case, NJ would be right.
In E/// case, I don’t know. Both are possible.